BiCMOS processes are used to form integrated circuits with bipolar and complementary metal-oxide semiconductor (CMOS) devices on a single substrate. BiCMOS integrated circuits are used in a variety of applications ranging from microprocessors and memory to communications devices. An advantage of BiCMOS integrated circuits relates to their ability to harness the best attributes of both MOS and bipolar devices. For example, BiCMOS devices may advantageously use characteristics of both MOS devices such as low power consumption and bipolar devices such as high switching speeds and/or regulation of high currents.
CMOS devices use complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. When arranged in an integrated circuit, CMOS logic comprises a collection of n-type MOSFETS (NMOSFETs) arranged in a pull-down network between an output node and a low-voltage power supply rail and a collection of p-type MOSFETs (PMOSFETs) arranged to form a pull-up network between the output and a high-voltage rail. By asserting or de-asserting inputs to the CMOS circuit, individual transistors in the pull-down network or the pull-up network become conductive, thereby providing a path from one of the voltage rails to the output. Because CMOS circuits only dissipate power when switching, they dissipate substantially less power than traditional NMOS logic circuits.
To improve the performance of bipolar and CMOS devices, some semiconductor fabrication processes have incorporated the use of strained Si or SiGe layers. The mechanical strain provided by such layers affords device designers the ability to modify the band gap characteristics and carrier mobilities of the devices. The incorporation of strained SiGe layers in bipolar devices has been prevalent, although the use of strained SiGe in CMOS devices has been less common. One reason for this is the fact that buried and surface channel CMOS fabrication is more complex than bulk silicon processing, which adds to the processing costs and reduces the device yield when fabricating such devices. For example, previous SiGe channel PMOSFETs used a selective epitaxial growth (SEG) process, which results in a more complex process than non-selective epitaxial growth.